http://hdl.handle.net/1893/27676
Appears in Collections: | Computing Science and Mathematics Conference Papers and Proceedings |
Author(s): | Bhowmik, Deepayan Wallace, Andrew Stewart, Robert Qian, Xinyuan Michaelson, Greg |
Contact Email: | deepayan.bhowmik@stir.ac.uk |
Title: | Profile driven dataflow optimisation of mean shift visual tracking |
Citation: | Bhowmik D, Wallace A, Stewart R, Qian X & Michaelson G (2014) Profile driven dataflow optimisation of mean shift visual tracking. In: 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP). 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP), Atlanta, Georgia, USA, 03.12.2014-05.12.2014. Piscataway, NJ, USA: IEEE. https://doi.org/10.1109/globalsip.2014.7032066 |
Issue Date: | 31-Dec-2014 |
Date Deposited: | 9-Aug-2018 |
Conference Name: | 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP) |
Conference Dates: | 2014-12-03 - 2014-12-05 |
Conference Location: | Atlanta, Georgia, USA |
Abstract: | Profile guided optimisation is a common technique used by compilers and runtime systems to shorten execution runtimes and to optimise locality aware scheduling and memory access on heterogeneous hardware platforms. Some profiling tools trace the execution of low level code, whilst others are designed for abstract models of computation to provide rich domain-specific context in profiling reports. We have implemented mean shift, a computer vision tracking algorithm, in the RVC-CAL dataflow language and use both dynamic runtime and static dataflow profiling mechanisms to identify and eliminate bottlenecks in our naive initial version. We use these profiling reports to tune the CPU scheduler reducing runtime by 88%, and to optimise our dataflow implementation that reduces runtime by a further 43% - an overall runtime reduction of 93%. We also assess the portability of our mean shift optimisations by trading off CPU runtime against resource utilisation on FPGAs. Applying all dataflow optimisations reduces FPGA design space significantly, requiring fewer slice LUTs and less block memory. |
Status: | VoR - Version of Record |
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Licence URL(s): | http://www.rioxx.net/licenses/under-embargo-all-rights-reserved |
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