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http://hdl.handle.net/1893/618| Appears in Collections: | Computing Science and Mathematics Conference Papers and Proceedings |
| Peer Review Status: | Refereed |
| Author(s): | He, Ji Turner, Kenneth J |
| Contact Email: | kjt@cs.stir.ac.uk |
| Title: | Specification and Verification of Synchronous Hardware using LOTOS |
| Editor(s): | Wu, Jianping Chanson, Samuel T Gao, Quiang |
| Citation: | He J & Turner KJ (1999) Specification and Verification of Synchronous Hardware using LOTOS. In: Wu J, Chanson ST & Gao Q (eds.) Formal Methods for Protocol Engineering and Distributed Systems. IFIP International Federation for Information Processing, Vol. 28. FORTE XII /PSTV XIX '99 IFIP TC6/WG 6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols and Protocol Specification, Testing and Verification, Beijing, China, 05.10.1999-08.10.1999. Amsterdam: Springer Verlag, pp. 295-312. http://www.springer.com/computer/artificial/book/978-0-7923-8646-9?detailsPage=toc |
| Issue Date: | 1999 |
| Date Deposited: | 16-Dec-2008 |
| Series/Report no.: | IFIP International Federation for Information Processing, Vol. 28 |
| Conference Name: | FORTE XII /PSTV XIX '99 IFIP TC6/WG 6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols and Protocol Specification, Testing and Verification |
| Conference Dates: | 1999-10-05 - 1999-10-08 |
| Conference Location: | Beijing, China |
| Abstract: | This paper investigates specification and verification of synchronous circuits using DILL (Digital Logic in LOTOS). After an overview of the DILL approach, the paper focuses on the characteristics of synchronous circuits. A more constrained model is presented for specifying digital components and verifying them. Two standard benchmark circuits are specified using this new model, and analysed by the CADP toolset (Cæsar/Aldébaran Development Package). |
| Status: | AM - Accepted Manuscript |
| Rights: | Published by Springer Verlag. The original publication is available at www.springer.com |
| URL: | http://www.springer.com/computer/artificial/book/978-0-7923-8646-9?detailsPage=toc |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| sync-lot.pdf | Fulltext - Accepted Version | 471.04 kB | Adobe PDF | View/Open |
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